Method and apparatus for interfacing with heterogeneous dual in-line memory modules

ABSTRACT

Described herein is a method and apparatus to interface a processor with a heterogeneous dual in-line memory module (DIMM). The method comprises determining an identity of a DIMM having data lanes; mapping the data lanes based on the determining of the identity of the DIMM; training input-output (I/O) transceivers in response to the mapping of the data lanes; and transferring data to and from the DIMM after training the I/O transceivers.

FIELD OF THE INVENTION

Embodiments of the invention relate generally to the field of processors. More particularly, embodiments of the invention relate to a method and an apparatus for interfacing a processor with a heterogeneous dual in-line memory module (DIMM).

BACKGROUND

Memory modules associated with computing devices at a high level are used for processing two general categories of data—graphics and general data. Examples of processing graphics include displaying an image on a screen while examples of processing general data other than graphics include processing financial data, word document processing, etc. Memory modules associated with processing graphics include a data mask (DM) DIMM (DM-DIMM). DM-DIMMs are specifically designed to improve memory usage of the dynamic access random memory (DRAMs) within the DM-DIMMs. Such DM-DIMMs have a specific pin-out interface that can only interface with a memory controller which is particularly designed to interface with a DM-DIMM. One reason for a custom memory controller to only interface with a DM-DIMM is to provide fast read and write operations to the DRAMs of the DM-DIMM when processing graphics. The fast read and write operations to the DRAMs of the DM-DIMM is accomplished by having an individual DM bit signal associated with the data lanes (or bus) for each DRAM of the DM-DIMM. One purpose of the DM bit signal is to mask the associated data lanes to avoid unnecessary write operations to the DRAM associated with the DM bit signal.

For example, if a small or a visually negligible portion of an image is to be updated with new data while the rest of the image is to remain the same, then a final new image does not need to be computed and re-stored in the DM-DIMM. In such a case, the DM bit signal for the DRAM is asserted to stop any update to the image data in the DRAM. Such a data mask bit signal saves intensive read and write operations on the DRAM because the final image did not need to change for its small or a visually negligible update.

Conversely, memory modules used for reading and storing general data other than graphics cannot be masked out because of a small or visually insignificant change. For example, if only one digit changes in a spreadsheet of financial data, such a digit cannot be masked out because it happens to be a small percentage of the entire financial data in the spreadsheet. Masking the entire financial data because of a change in one digit may result in an incorrect financial analysis based on the masked financial data. Such memory modules may include error correction capability via error correction code (ECC). The ECC may be used to scrub any incorrect data in the DRAMs of the DIMM so that the data in the DIMM is always correct. Such memory modules are called ECC-DIMMs and have a specific pin-out interface to interface with particular memory controllers called ECC memory controllers.

As computer form/structure is becoming compact, separate memory controllers on a computer motherboard to interface with different/heterogeneous types of DIMMs result in larger motherboard size area. Examples of heterogeneous DIMMs include DM-DIMM, ECC-DIMM, etc. Furthermore, a user of a computer is not able to interface the memory controller of the computer with different/heterogeneous DIMMs because the memory controller has a specific pin-out interface and logic (hardware and/or software) to interface with only one kind of DIMM rather than heterogeneous DIMMs. Plugging a DM-DIMM with a controller designed for ECC-DIMM only or vice versa may result into catastrophic system failure from, for example, power/ground signal shorting caused by different pin interface for power/ground pins for DM-DIMM and ECC-DIMM.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.

FIG. 1 illustrates a high level system architecture of a memory controller to interface with a heterogeneous dual in-line memory module (DIMM), according to one embodiment of the invention.

FIG. 2 is a memory controller operable to interface with the heterogeneous DIMM, according to one embodiment of the invention.

FIG. 3A illustrates the memory controller for interfacing with a data mask (DM) DIMM (DM-DIMM), according to one embodiment of the invention.

FIG. 3B illustrates the memory controller for interfacing with an error correction code (ECC) DIMM (ECC-DIMM), according to one embodiment of the invention.

FIG. 3C is a connector pin-out mapping caused by the memory controller to interface with either a DM-DIMM or an ECC-DIMM, according to one embodiment of the invention.

FIG. 3D is another connector pin-out mapping caused by the memory controller to interface with either a DM-DIMM or an ECC-DIMM, according to one embodiment of the invention.

FIG. 4A illustrates a high level flow chart for interfacing the memory controller with a heterogeneous DIMM, according to another embodiment of the invention.

FIG. 4B illustrates a flow chart for determining an identification of a heterogeneous DIMM for interfacing the memory controller with the heterogeneous DIMM, according to one embodiment of the invention.

FIG. 4C illustrates a flow chart for mapping signals to the input-output (I/O) transceivers of the memory controller to interface with a heterogeneous DIMM, according to one embodiment of the invention.

FIG. 5 illustrates a system with a machine-readable medium having computer executable instructions stored on the medium for interfacing the memory controller with a heterogeneous DIMM, according to one embodiment of the invention.

DETAILED DESCRIPTION

Embodiments of the invention relate to a method and apparatus for interfacing a processor with heterogeneous dual in-line memory modules (DIMMs). For illustrating the invention, the embodiments of the invention discuss two types of DIMMs that are referred to as heterogeneous DIMMs. As mentioned in the background section, the first type of DIMM is a data mask (DM) DIMM (DM-DIMM) while the second type of DIMM is an error correction code (ECC) DIMM (ECC-DIMM). The embodiments of the invention are not limited to the two types of DIMMs. Other types of DIMMs can be used to interface with the processor without changing the principal of operation of the embodiments of the invention.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present invention. It will be apparent, however, to one skilled in the art, that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present invention.

Note that in the corresponding drawings of the embodiments signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction any may be implemented with any suitable type of signal scheme, e.g., differential pair, single-ended, etc.

FIG. 1 illustrates a high level system architecture 100 of a memory controller 101 (also referred to as a processor or a device) to interface with a heterogeneous DIMM 102, according to one embodiment of the invention. In one embodiment, the memory controller 101 is operable to interface and communicate with the heterogeneous DIMM 102 via interconnects 107. In one embodiment, the memory controller 101 is operable to interface and communicate with the heterogeneous DIMM 102 after determining an identification of the heterogeneous DIMM 102 via a serial presence detect (SPD) identification 106.

In one embodiment, the SPD identification 106 contains an identification that signifies that the heterogeneous DIMM 102 is a DM-DIMM having one or more DRAM units 105. In another embodiment, the SPD identification 106 contains an identification that signifies that the heterogeneous DIMM 102 is an ECC-DIMM having one or more DRAM units 105 and an ECC DRAM unit (not shown) to scrub the DRAM units 105 for errors in the DRAM bits. In other embodiments, the SPD identification 106 contains an identification that signifies that the heterogeneous DIMM 102 is a DIMM other than a DM-DIMM and an ECC-DIMM.

In one embodiment, the memory controller 101 includes one or more logic units 103 (hardware and/or software) to interface with the heterogeneous DIMM 102 via a connector 104. In one embodiment, the connector 104 resides independently on the motherboard and is not integrated within the memory controller 101 shown in FIG. 1. In other embodiments, the connector 104 is functionally fully integrated within the memory controller 101.

In one embodiment, the one or more logic units 103 are operable to read the SPD identification 106 and then map (which is discussed later) the signals to interface with the heterogeneous DIMM 102 based on the SPD identification 106. In one embodiment, all signals to the heterogeneous DIMM 102 are mapped by the logic unit 103 according to the SPD identification 106. In other embodiments, only a subset of signals to the heterogeneous DIMM 102 is mapped by the logic unit 103 according to the SPD identification 106. In one embodiment, the memory controller 101 is incorporated within a central processing unit (CPU). In other embodiments, the memory controller 101 is an independent processor (also called micro-controller) separate from the CPU but communicatively coupled with the CPU.

FIG. 2 illustrates is a detailed block diagram 200 showing components of the memory controller 101, according to one embodiment of the invention. In one embodiment, the memory controller 101 is operable to electrically couple with the heterogeneous DIMM (102 of FIG. 1) via connector pins 108 of a connector 104 and data lanes or buses (not shown). In one embodiment, the connector pins 108 are driven by input-output (I/O) transceivers 206 that send and receive data to and from the heterogeneous DIMM (102 of FIG. 1). In one embodiment, a training logic unit 205 is operable to train the I/O transceivers 206 based on the SPD identification 201 (same as 106 of FIG. 1) received by the logic unit 202 from the heterogeneous DIMM (102 of FIG. 1) via the connector 104. In one embodiment, the training logic unit 205 is operable to provide training signals 207 to the I/O transceivers 206 after the logic unit 202 informs the training logic unit 205 via signal path 209 that the heterogeneous DIMM 102 is indentified from its SPD identification 201.

In one embodiment, the logic unit 202 is operable to read the SPD identification 201 and to determine a select signal 203 for a multiplexer 204. In one embodiment, the multiplexer 204 comprises a plurality of multiplexers to output signal 210 (which is a plurality of signals) for the I/O transceivers 206. In one embodiment, the input signal 208 (which is a plurality of signals) is mapped to the I/O transceivers 206 in response to the select signal 203 of the multiplexer 204.

The term map refers to assigning or re-assigning an input signal from among the input signals 208 to a particular I/O transceiver from among the I/O transceivers 206 so that the connector pin 108 drives a signal which is expected by the heterogeneous DIMM (102 of FIG. 1). The expected signal refers to a signal which the heterogeneous DIMM comprehends. For example, an ECC-DIMM does not comprehend a DM bit signal because a DM bit signal is not used by the ECC-DIMM architecture and so an ECC-DIMM does not expect a DM bit signal to be received by the ECC-DIMM.

In one embodiment, after the input signals 208 are mapped to particular I/O transceivers from among the I/O transceivers 206, the training logic unit 205 begins a sequence of operations to adjust signal characteristics of the output signal to be sent to the heterogeneous DIMM (102 of FIG. 1). In one embodiment, the training logic unit 205 is operable to position a data strobe signal transmitted from the memory controller 101 to the heterogeneous DIMM (102 of FIG. 1) to be near or at the center of a corresponding data signal. FIG. 4C, which is discussed later, provides details of the training sequence executed by the training logic unit 205, according to one embodiment of the invention.

In one embodiment, the training logic unit 205 is operable to align a data strobe signal to a center of corresponding signals on the data lanes, wherein the data lanes are interconnect buses between the heterogeneous DIMM (102 of FIG. 1) and the connector pins 108. In one embodiment, the training logic unit 205 is operable to adjust an eye width and height of signals on the data lanes by adjusting the drive strength of the I/O transceivers 206. In one embodiment, the training logic unit 205 is operable to adjust the delays associated with signals on the data lanes so that signals on all data lanes have substantially equal flight times. In one embodiment, the training logic unit 205 is operable to adjust the termination impedance of the I/O transceivers 206. In one embodiment, the training logic unit 205 is operable to train the I/O transceivers 206 according to well known methods.

The following embodiments discuss two types of heterogeneous DIMMs—DM-DIMM and ECC-DIMM—so as not to obscure the embodiments of the invention. As mentioned above, other types of heterogeneous DIMMs may be used without changing the essence of the embodiments of the invention.

In one embodiment, the logic unit 202 is operable to identify that the SPD identification 201 of the heterogeneous DIMM (102 of FIG. 1) is a DM-DIMM. In such an embodiment, the logic unit 202 is operable to send a select signal 203 to the multiplexer 204 so that a DM bit signal is assigned to a bit lane reserved for a subset of the data lanes for an ECC DRAM unit (323 of FIG. 3B). As mentioned above, the term data lane refers to an interconnect bus between the heterogeneous DIMM (102 of FIG. 1) and the memory controller 101. FIG. 3A, which is discussed later, provides a functional view of how the data lanes are reassigned for a DM-DIMM compared to an ECC-DIMM, according to one embodiment of the invention.

In one embodiment, the logic unit 202 is operable to identify that the SPD identification 201 of the heterogeneous DIMM (102 of FIG. 1) is an ECC-DIMM. In such an embodiment, the logic unit 202 is operable to send a select signal 203 to the multiplexer 204 so that a subset of the data lanes from among the data lanes is assigned to an ECC DRAM unit (323 of FIG. 3B) of the ECC-DIMM (324 of FIG. 3B). FIG. 3B, which is discussed later, provides a functional view of how the data lanes are reassigned for an ECC-DIMM compared to a DM-DIMM, according to one embodiment of the invention. FIG. 3C and FIG. 3D, which are also discussed later, provide details of signal mapping between a DM-DIMM and an ECC-DIMM, according to one embodiment of the invention.

While the embodiments herein discuss the logic units that map/assign input signals 208 to output signals 210 for the I/O transceivers 206 based on the SPD identification 201 of the heterogeneous DIMM, a similar logic (not shown) is used to remap signals from the heterogeneous DIMM based on the SPD identification 201. In one embodiment, the above logic (not shown in figures) remaps signals coming from the heterogeneous DIMM via the connector 104 and the I/O transceivers 206 into the memory controller 101 for processing.

FIG. 3A illustrates a system level block architecture 300 with a memory controller 301 for interfacing with a DM-DIMM 302, according to one embodiment of the invention. In such an embodiment, the heterogeneous DIMM (102 of FIG. 1) is a DM-DIMM 302. In one embodiment, the DRAMs 311 a-h of the DM-DIMM 302 are operable to receive data signals 309 a-h and corresponding DM bit signals 310 a-h, respectively. While the embodiment of FIG. 3A shows 8 DRAM units per DM-DIMM, fewer or more DRAM units may be used that can be mapped with the memory controller 301 via the same method and apparatus discussed herein.

In one embodiment, the controller logic unit 303 (103 of FIG. 1) of the memory controller 301 is operable to receive an SPD identification 312 from the DM-DIMM 302 via an interconnect 201. In one embodiment, the logic unit 202 of the controller logic unit 303 is operable to determine a select signal 203 to map each input signal from among the input signals 308 as output signals 307 to a particular I/O transceiver from among the I/O transceivers 305 a-h, 306, and 313 of the memory controller 301. While the embodiment of FIG. 3A shows 10 sets of I/O transceivers (305 a-h, 306, and 313), fewer or more sets of I/O transceivers may be used to interface with a heterogeneous DIMM. In one embodiment, each set of I/O transceivers (305 a-h, 306, and 313) has one or more I/O transceivers.

In one embodiment, the connector interface 304 is a universal connector interface. In such an embodiment, the connector interface 304 remains the same, i.e., same number of pins at the same location with same physical form/structure to the external world, while the I/O transceivers 305 a-h of the memory controller 301 are operable to send and receive different signals to and from the heterogeneous DIMM depending on the SPD identification 312 of the heterogeneous DIMM.

In one embodiment, the multiplexer 204 is operable to assign each output signal from among the output signals 307 to individual sets of I/O transceivers 305 a-h so that each DRAM 311 a-h receives a corresponding data bus 309 a-h with a corresponding DM bit signal 310 a-h (from the bus 310). In one embodiment, the assignment of the I/O transceivers 305 a-h, 306, and 313 is done so that the I/O transceivers in the middle i.e., 306 is assigned to drive DM bit signals 309 a-h to the heterogeneous DIMM if the heterogeneous DIMM is a DM-DIMM and to drive ECC signals (not shown) to a heterogeneous DIMM if the heterogeneous DIMM is an ECC-DIMM. By assigning the I/O transceivers 306 in the middle, fewer overall signals need to be reassigned between an ECC-DIMM and a DM-DIMM compared to re-assigning the entire signals when switching between an ECC-DIMM to a DM-DIMM.

In one embodiment, the I/O transceivers 313 which are reserved for address and control signals remain unchanged whether the heterogeneous DIMM is a DM-DIMM or an ECC-DIMM. In such an embodiment, the number of re-assigned signals from among the output signals 307 is reduced compared to re-assigning all output signals 307 caused by switching between a DM-DIMM to an ECC-DIMM or vice versa. In another embodiment, all the I/O transceivers 305 a-h, 306, and 313 are reassigned different output signals 307 from the multiplexer 204 so that a proper communicative connection of the memory controller 301 with the heterogeneous DIMM (102 of FIG. 1) is established.

In one embodiment, once the output signals 307 are assigned/mapped to a particular I/O transceiver from among the I/O transceivers 305 a-h, 306, and 313, the training logic unit 205 of FIG. 2 trains the I/O transceivers 305 a-h, 306, and/or 313 to meet a particular or pre-determined signal-integrity constraint (e.g., overshoot, undershoot, Vol, Voh, eye width and height, etc.), power constraint (e.g., power consumption), and timing constraint (e.g., valid time, setup time, hold time, etc.) of the signals 309 a-h, 310 a-h, 314.

FIG. 3B illustrates a system architecture 320 showing how the signals on the data lanes are reassigned for an ECC-DIMM compared to a DM-DIMM of FIG. 3A, according to one embodiment of the invention. The term data lanes and signals on the data lanes are used interchangeably in the description. The process of mapping signals on data lanes generally refers to identifying and assigning specific signals to be driven on those data lanes. In one embodiment, the logic unit 202 is operable to determine that the heterogeneous DIMM (102 of FIG. 1) is an ECC-DIMM 324. In one embodiment, the ECC-DIMM 324 includes one or more DRAMs 311 a-h and an ECC DRAM unit 323 to correct any error in data value in the DRAMs 311 a-h. In one embodiment, the ECC-DIMM 324 receives no DM-bit signals for reasons discussed in the background section.

In one embodiment, after the logic unit 202 determines that the heterogeneous DIMM is an ECC-DIMM 324 by reading the SPD identification 312, the logic unit 202 generates a select signal 203. In one embodiment, the select signal 203 is operable to assign/map the input signals 308 as output signals 307 so that the memory controller 301 properly communicates with the ECC-DIMM 324.

In one embodiment, proper communication between the memory controller 301 and the ECC-DIMM 324 occurs by assigning/mapping the output signals 307 to individual sets of I/O transceivers 305 a-h, 306, and 313 for communicating with the DRAMs 311 a-h and an ECC DRAM unit 323. Compared to the embodiments of FIG. 3A, signals 310 from the I/O transceivers 306 of FIG. 3B are all assigned to the ECC DRAM unit 323 and not to the DRAMs 311 a-h as DM bit signals. In such an embodiment, the DRAMs 311 a-h are operable to receive the output signals 307 via signals 321 a-h from I/O transceivers 305 a-h, respectively. In this embodiment, the ECC signals 310 are generated by the I/O transceivers 306 which reside substantially in the middle of the column of I/O transceivers 305 a-h, 306, and 313.

One reason for assigning/mapping signals from the output signals 307 for ECC purposes to I/O transceiver 306 is the location of the ECC DRAM unit 323 within the ECC-DIMM 324—the ECC DRAM unit 323 is substantially in the middle of the ECC-DIMM 324 and so the signals 310 for ECC purposes from among the output signals 307 are assigned/mapped to the I/O transceiver 306 which is also substantially in the middle of the memory controller 301. In such an embodiment, the ECC signals 310 have a shorter distance to travel from the I/O transceivers 306 to the ECC DRAM unit 323. The shorter distance allows for faster arrival time of ECC signals 310 and relatively easier signal timing adjustment by adding delays to the ECC signals 310 to meet the timing constraints.

While the embodiment of FIG. 3B shows 10 sets of I/O transceivers (305 a-h, 306, and 313), fewer or more sets of I/O transceivers may be used to interface with a heterogeneous DIMM. Similarly, while the embodiment of FIG. 3B shows 8 DRAM units (311 a-h) per ECC-DIMM 324, fewer or more DRAM units may be used that can be mapped with the memory controller 301 via the same method and apparatus discussed herein.

In one embodiment substantially all output signals 307 to the I/O transceivers 305 a-h are reassigned according to the identification 201 of the heterogeneous DIMM (102 of FIG. 1).

In one embodiment, the timing logic unit 205 of FIG. 2 (not shown in FIGS. 3A-B) is operable to instruct the multiplexer 204 to reassign signals previously assigned to I/O transceivers 305 e to I/O transceivers 305 d to meet signal constraints such as timing constraints and signal integrity constraints.

FIG. 3C is a detailed Table 340 showing reassignment of the output signals 307 based on the SPD identification of the heterogeneous DIMM 102 of FIG. 1, according to one embodiment of the invention. Table 340 shows the functional pin-outs from the memory controller 301 of FIGS. 3A-B when an ECC-DIMM is replaced with a DM-DIMM or vice versa, according to one embodiment of the invention. In one embodiment, Table 340 is pin-out of a small-outline DIMM (SO DIMM) having 244 pins. The pins on the front and back of the DIMM are identified as pins in columns 341 and 342 respectively. Column 343 of the Table 340 illustrates the functional attributes of the pins if the heterogeneous DIMM is an ECC-DIMM while column 344 of the Table 340 illustrates a corresponding functional attribute of the pins if the ECC-DIMM is replaced with a DM-DIMM. In one embodiment, the functional attributes of the pins change between the ECC-DIMM and the DM-DIMM via the memory controller 101.

In one embodiment, interconnects for the re-mapped data bit signals (i.e., DQ and DQS signals) are matched within a distance of +/−25 mils on the motherboard. In one embodiment, the multiplexing by the multiplexer 204 is done so that there are 72 fully matched DQ signal bits with corresponding 9 associated DQS (strobe) signals. In one embodiment, when the DM-DIMM is replaced with an ECC-DIMM, the memory controller 101 regroups the DQ bits via the multiplexer 204 while skipping the DM bit signals as shown in FIG. 3D.

FIG. 3D illustrates a connector pin mapping by the memory controller 101 with respect to specific signals from Table 340 of FIG. 3C, according to one embodiment of the invention. The connector pin mapping is shown by Table 350. The left half 351 of the Table 350 illustrates the functional mapping/assignment of connector pins 108 caused by the memory controller 101 when swapping an ECC-DIMM with a DM-DIMM, according to one embodiment of the invention. In such an embodiment, the memory controller 101 is operable to re-assign the data lanes reserved for ECC signals (310 in FIG. 3A) to be used as data mask signals (310 a-h in FIG. 3A). The right half 352 of the Table 350 illustrates the functional mapping/assignment of connector pins 108 caused by the memory controller 101 when swapping a DM-DIMM with an ECC-DIMM, according to one embodiment of the invention. In such an embodiment, the memory controller 101 is operable to re-assign specific data lanes previously used by the DM-DIMM to be used as ECC signals (310 in FIG. 3B). The embodiments of FIGS. 3C-D are not limiting embodiments. Other embodiments that map/re-assign data lanes different from the ones shown in Tables 340 and 350 can be used without changing the essence of the embodiments of the invention.

FIGS. 4A-C illustrate a flow chart for interfacing the memory controller 101 of FIGS. 1-2 with a heterogeneous DIMM 102 of FIG. 1, according to another embodiment of the invention. The flow charts are described with reference to the embodiments of FIG. 1-3.

FIG. 4A illustrates a high level flow chart 400 for interfacing the memory controller 101 of FIG. 1-2 with a heterogeneous DIMM 102 of FIG. 1, according to another embodiment of the invention. At block 401, the memory controller 101 determines the identity of the heterogeneous DIMM via the SPD identification 201. At block 402, the logic unit 202 maps the input signals 208 as output signals 307 via the multiplexer 204 based on the identity of the heterogeneous DIMM. At block 403, the I/O transceivers (206 of FIG. 2 and 305 a-h, 306, and/or 313 of FIGS. 3A-B) are trained by the training logic unit 205. Once a training sequence of the training logic unit 205 completes, at block 404 the heterogeneous DIMM 102 operates in a normal fashion i.e., data is transferred as needed to and from the heterogeneous DIMM.

FIG. 4B illustrates a flow chart 410 for determining an identification of a heterogeneous DIMM 102 for interfacing the memory controller 101 with the heterogeneous DIMM 102, according to one embodiment of the invention. At block 401 a the SPD identification from the heterogeneous DIMM is read by the logic unit 202 of the memory controller 101. In this flow chart, two embodiments of heterogeneous DIMM 101 are considered—DM-DIMM and ECC-DIMM. Other types of DIMMs can be used with the memory controller 101 without changing the essence of the embodiments of the invention. If the memory controller 101 determines that the SPD identification 106 read at block 401 a is for a DM-DIMM, then block 411 is followed which starts the method at block 402 of FIG. 4A and FIG. 4C.

If the memory controller 101 determines that the SPD identification 106 read at block 412 is for an ECC-DIMM, then at block 412 a subset of data lanes/buses for ECC purposes (310) is assigned to the ECC DRAM unit 323 of the ECC-DIMM as discussed with reference to FIGS. 3A-B. At block 413, the method continues from block 403 of FIG. 4A.

FIG. 4C illustrates a flow chart 402 for mapping a heterogeneous DIMM 102 to the memory controller 101, according to one embodiment of the invention. After the multiplexer 204 assigns signals from among the output signals 307 to different I/O transceivers based on the SPD identification 106 of the heterogeneous DIMM 102, at block 402 a, a data strobe signal (a DQS signal in FIG. 3C) is aligned with associated signals on data lanes (DQ signals 309 a-h, 331 a-h, and 331 a-h of FIG. 3A-B) by positioning the data strobe signal to latch the associated signals of data lanes. One method for aligning the data strobe signal with associated signals on data lanes is described in U.S. Pat. No. 7,307,900.

At block 402 b, if the heterogeneous DIMM is a DM-DIMM then a DM bit is assigned to a bit lane reserved for the subset of data lanes for ECC. As a result of this assignment, in one embodiment the DM bit signals are transmitted to the DM-DIMM via the subset of data lanes reserved for ECC. As discussed with reference to FIG. 3A, ECC signals 310 are mapped to DM bits signals 310 a-h.

At block 402 c, the DM bit signals 310 a-h are aligned with corresponding data signals (for example, DQ signals in FIG. 3C) for the corresponding DRAMs 311 a-h, wherein the data signals are aligned at block 402 a with a corresponding data strobe signal (for example, DQS signals in FIG. 3C). In one embodiment, the DM bit signals 310 a-h are delayed with respect to the data signals 309 a-h associated with each of the DRAMs so that the DM bit signals 310 a-h are aligned with respect to corresponding data signals 309 a-h. In other embodiments, the data signals 309 a-h and corresponding data strobe signals are delayed so that the DM bit signals 310 a-h are aligned with respect to corresponding data signals 309 a-h.

The term delay refers broadly to increasing and/or reducing delay in time of the signal. The term align refers broadly to position the data signals and the DM bit signal so that timing margin/requirements are met. In one embodiment, phase interpolators (not shown) are used to delay the data signals relative to the DM bit signals or vice versa.

FIG. 5 illustrates a system 500 with a machine-readable medium 503 having computer executable instructions 504 stored on the medium 503 for interfacing the memory controller 101 with a heterogeneous DIMM 102, according to one embodiment of the invention. Referring back to FIGS. 1-4, in one embodiment the memory controller 101 is operable to map and align the signals from among the output signal 307 based on the computer executable instructions 504. For example, the logic unit 202 and the training logic unit 205 of FIG. 2 are programmable via the computer-executable instructions 504 to map and align the signals from among the output signal 307. The machine-readable storage medium 503 may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or other type of machine-readable storage media suitable for storing electronic or computer-executable instructions. For example, embodiments of the invention may be downloaded as a computer program which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic “may,” “might,” or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.

While the invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, in one embodiment the controller 101 is functionally integrated within a general purpose CPU and does not exist as a separate processor on the motherboard. The embodiments of the invention are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims. 

We claim:
 1. A method comprising: determining an identity of a dual in-line memory module (DIMM) having data lanes, wherein the identity of the DIMM indicates whether the DIMM is a data-mask (DM) DIMM (DM-DIMM) or an error correction code (ECC) DIMM (ECC-DIMM), wherein the: DM-DIMM includes an interface for a DM bit associated with the data lanes; and ECC-DIMM includes an interface for an ECC bit, wherein the interfaces of the DM-DIMM and the ECC-DIMM are different from one another; mapping the data lanes based on the determining of the identity of the DIMM; training input-output (I/O) transceivers in response to the mapping of the data lanes by: centering a strobe signal relative to signals on corresponding data lanes; and adjusting an eye width and height for each of the signals on the corresponding data lanes by adjusting a drive strength of the I/O transceivers; and transferring data to and from the DIMM after training the I/O transceivers.
 2. The method of claim 1, wherein mapping the data lanes based on the determining of the identity of the DIMM comprises: multiplexing the data lanes by a controller coupled with the DIMM; assigning a DM bit from among the data lanes to each dynamic random access memories (DRAMs) of the DIMM if the identity of the DIMM is the DM-DIMM; and assigning a subset of the data lanes for ECC if the identity of the DIMM is the ECC-DIMM.
 3. The method of claim 2, wherein assigning the DM bit comprises assigning the DM bit to a bit lane reserved for the subset of the data lanes for ECC.
 4. The method of claim 2, wherein assigning the DM bit comprises: aligning a data strobe signal with associated signals of data lanes by positioning the data strobe signal to latch the associated signals of data lanes; assigning the DM bit to a bit lane reserved for the subset of the data lanes for ECC, the assigned DM bit to correspond to each of the DRAMs of the DM-DIMM; and aligning a DM bit signal of the assigned DM bit with the associated signals of data lanes by adjusting a delay of the DM bit signal with respect to a data signal from among the associated signals of data lanes.
 5. The method of claim 2, wherein assigning the subset of the data lanes for ECC comprises assigning the subset of the data lanes to an ECC DRAM unit of the DIMM.
 6. The method of claim 1, wherein the DIMM is a small-outline (SO) DIMM.
 7. The method of claim 1, wherein determining the identity of the DIMM comprises reading a serial presence detect (SPD) identification from the DIMM.
 8. An apparatus comprising: input-output (I/O) transceivers operable to send and receive data to and from a dual in-line memory module (DIMM) via data lanes; a logic unit operable to determine an identity of the DIMM, wherein the identity of the DIMM indicates whether the DIMM is a data-mask (DM) DIMM (DM-DIMM) or an error correction code (ECC) DIMM (ECC-DIMM), wherein the: DM-DIMM includes an interface for a DM bit associated with the data lanes; and ECC-DIMM includes an interface for an ECC bit, and wherein the interfaces of the DM-DIMM and the ECC-DIMM are different from one another; and a multiplexer, coupled with the logic unit and with the I/O transceivers, operable to map the data lanes based on the identity of the DIMM.
 9. The apparatus of claim 8, wherein the logic unit is operable to read a serial presence detect (SPD) identification from the DIMM to determine whether the DIMM is the DM-DIMM or the ECC-DIMM.
 10. The apparatus of claim 8, wherein the multiplexer is operable to: assign a DM bit from among the data lanes to each dynamic random access memories (DRAMs) of the DIMM if the DIMM is the DM-DIMM; and assign a subset of the data lanes for ECC if the DIMM is the ECC-DIMM.
 11. The apparatus of claim 10, wherein the multiplexer is operable to assign the DM bit to a bit lane reserved for the subset of the data lanes for ECC.
 12. The apparatus of claim 10 further comprising a training unit operable to: align a data strobe signal with associated signals of data lanes by positioning the data strobe signal to latch the associated signals of data lanes; assign the DM bit to a bit lane reserved for the subset of the data lanes for ECC, the assigned DM bit to correspond to each of the DRAMs of the DM-DIMM; and align a DM bit signal of the assigned DM bit with the associated signals of data lanes by adjusting a delay of the DM bit signal with respect to a data signal from among the associated signals of data lanes.
 13. The apparatus of claim 10, wherein the multiplexer is operable to assign the subset of the data lanes for ECC by assigning the subset of the data lanes to an ECC DRAM unit of the ECC-DIMM.
 14. The apparatus of claim 8 further comprises a training logic unit operable to: train the I/O transceivers by centering a strobe signal relative to signals on corresponding data lanes; and adjust an eye width and height for each of the signals on the corresponding data lanes by adjusting a drive strength of the I/O transceivers.
 15. The apparatus of claim 8, wherein the DIMM is a small-outline (SO) DIMM.
 16. A system comprising: a dual in-line memory module (DIMM); and a controller coupled with the DIMM via data lanes, the controller further comprising: input-output (I/O) transceivers operable to send and receive data to and from the DIMM via data lanes; a logic unit operable to determine an identity of the DIMM, wherein the identity of the DIMM indicates whether the DIMM is a data-mask (DM) DIMM (DM-DIMM) or an error correction code (ECC) DIMM (ECC-DIMM), wherein the: DM-DIMM includes an interface for a DM bit associated with the data lanes; and ECC-DIMM includes an interface for an ECC bit, and wherein the interfaces of the DM-DIMM and the ECC-DIMM are different from one another; and a multiplexer, coupled with the logic unit and with the I/O transceivers, operable to map the data lanes based on the identity of the DIMM.
 17. The system of claim 16, wherein the controller is operable to interface with either the DM-DIMM or the ECC-DIMM.
 18. The system of claim 16, wherein the multiplexer is operable to: assign a DM bit from among the data lanes to each dynamic random access memories (DRAMs) of the DIMM if the DIMM is the DM-DIMM; and assign a subset of the data lanes for ECC if the DIMM is the ECC-DIMM.
 19. The system of claim 18, wherein the multiplexer is operable to assign the DM bit to a bit lane reserved for the subset of the data lanes for ECC.
 20. The system of claim 18 further comprising a training unit operable to: align a data strobe signal with associated signals of data lanes by positioning the data strobe signal to latch the associated signals of data lanes; assign the DM bit to a bit lane reserved for the subset of the data lanes for ECC, the assigned DM bit to correspond to each of the DRAMs of the DM-DIMM; and align a DM bit signal of the assigned DM bit with the associated signals of data lanes by adjusting a delay of the DM bit signal with respect to a data signal from among the associated signals of data lanes.
 21. The system of claim 18, wherein the multiplexer is operable to assign the subset of the data lanes for ECC by assigning the subset of the data lanes to an ECC DRAM unit of the ECC-DIMM.
 22. The system of claim 16 further comprising a training logic operable to: train the I/O transceivers by centering a strobe signal relative to signals on corresponding data lanes; and adjust an eye width and height for each of the signals on the corresponding data lanes by adjusting a drive strength of the I/O transceivers.
 23. The system of claim 22, wherein the training logic unit 205 is operable to adjust the delays of signals on each of the data lanes to cause the signals to have equal flight times.
 24. The system of claim 16, wherein the DIMM is a small-outline (SO) DIMM. 